The present invention relates to techniques for transmitting data from a memory device through a parallel interface, and more particularly, to techniques for transmitting data from a memory device using a parallel sequential read mode.
Programmable integrated circuits such as field programmable gate arrays (FPGAs) are configured (i.e., programmed) using configuration data. Configuration data used to configure a programmable circuit can be stored in an external memory device such as a FLASH memory device.
Configuration data can be transferred in serial or in parallel from a FLASH memory device to an FPGA. For parallel data transfer, some types of prior art FPGAs interface directly with the FLASH memory device using 35 input/output (IO) pins on the FPGA.
The FPGA interfaces directly with the FLASH memory using Asynchronous Read Mode. In this scenario, 23 address pins are provided by the FPGA. In addition to the 23 address pins, 8 data pins and 4 control pins (total 35) are consumed on the FPGA to implement this data transfer system.
Other types of prior art FPGAs interface with the FLASH device via a microcontroller. The microcontroller is a discrete chip or a controller chip that is packaged together with the FLASH memory device in a single package. If the microcontroller is a discrete chip, the microcontroller sits between the FPGA and the FLASH memory device.
The microcontroller reads data from the FLASH device, then passes the data to the FPGA. Specifically, the microcontroller generates memory addresses and transfers the memory addresses to the FLASH device. The FLASH device then transfers data bits that are stored at the received memory addresses to the FPGA in parallel.
The FLASH device only transfers data bits to the FPGA in response to memory addresses received from the microcontroller. This type of data transfer is referred to as asynchronous read mode. Because each set of data bits needs to be individually addressed by the microcontroller, data transfer from the FLASH device to the FPGA is slow.
Therefore, there is a need to provide faster techniques for transferring configuration data from an external memory device to a programmable integrated circuit that requires less pins.
There is also a need to eliminate the microcontroller from prior art configuration data transfer techniques and to have the FPGA and FLASH interface directly to save board space, device cost (for the microcontroller), and development time to write FLASH-FPGA interface code for the microcontroller.